In the technique investigated by the present inventors, the following techniques may be considered, for example, in a semiconductor device having a phase change memory. The storage device uses chalcogenide materials such as Ge—Sb—Te system and an Ag—In—Sb—Te system at least containing antimony (Sb) and tellurium (Te) (or phase change material) as the material for a storage layer. Further, a diode is used as a selection device. Information is stored by controlling the crystal state of the chalcogenide material by Joule heat. The stored information is read out by detecting the resistance value which is different between an amorphous state and a crystalline state by a current. The resistance is high in the amorphous state and resistance is low in the crystalline state. The device characteristic of the phase change memory using the chalcogenide material and the diode described above are described for example, in IEEE International Solid-State Circuits Conference, Digest of Technical papers, FIG. 26.1.5 in USA. Further, when the structure of the resistance device is made smaller in the phase change memory, electric power necessary for the change of state of a phase change film is decreased as described in IEEE International Electron Devices meeting, Technical Digest, (US) 2001, pp. 803-806, FIG. 7. Accordingly, the phase change memory is suitable to refinement in view of the principle and studies therefor have been conducted vigorously.
As a method of making the integration degree higher in the memory utilizing such resistance change type devices, Japanese Unexamined Patent Publication No. 2004-272975 and Japanese Unexamined Patent Publication No. 2009-124175 disclose a serial/parallel type memory cell array in which multiple memory cells each having a transistor as a selection device and a resistance change type device connected in parallel are connected in series. This is a memory cell array configuration capable of obtaining a cell area of 4F2 physical area to the minimum of feature size F, which is a structure suitable for high integration. Further, Japanese Unexamined Patent Publication No. 2008-160004 describes a structure in which the serial-parallel type memory cell array is formed in a direction vertical to a silicon substrate. By stacking memory cells, increase in the capacitance is further progressed.
Documents relevant to the present invention include IEEE International Solid-State Circuits Conference, Digest of Technical papers. The document discloses a method of manufacturing an NAND type flash memory with a less number of steps per layer by depositing gate electrode materials and insulating films each in plurality, forming multiple holes penetrating all layers by collective fabrication in the stacked structure and depositing and fabricating a charge trap layer containing a silicon nitride film, a tunnel insulating film, and polysilicon as a channel inside the holes.